1. Field of the Invention
The present invention relates to a level shift circuit, and more particularly relates to a level shift circuit used for a low temperature poly-silicon panel.
2. Description of the Related Art
Low temperature poly-silicon (LTPS) panels have the advantage of having short response times, being very bright and having high resolutions. Therefore, manufacturers are increasingly investing resources into the development of LTPS devices. With rapid development in technology, LTPS panels will possibly become very popular and replace the mainstream thin film transistor liquid crystal display (TFT-LCD) used in flat panel displays (FPD).
FIG. 1 is a circuit diagram depicting a level shift circuit of the prior art. The level shift circuit has a first PMOS transistor 140, a second PMOS transistor 130, a first NMOS transistor 110, and a second NMOS transistor 120.
A source of the first PMOS transistor 140 is coupled to a power source terminal (VDDA) 190, a gate of the first PMOS transistor 140 is coupled to a second output terminal 135, a drain of the first PMOS transistor 140 is coupled to a first output terminal 145. A source of the second PMOS transistor 130 is coupled to the power source terminal (VDDA) 190, a gate of the second PMOS transistor 130 is coupled to the first output terminal 145, a drain of the second PMOS transistor 130 is coupled to the second output terminal 135. A drain of the first NMOS transistor 110 is coupled to the second output terminal 135, a gate of the first NMOS transistor 110 is coupled to a first input terminal 115, a source of the first NMOS transistor 110 is coupled to a ground terminal (VSSA) 180. A drain of the second NMOS transistor 120 is coupled to the first output terminal 145, a gate of the second NMOS transistor 120 is coupled to a second input terminal 125, a source of the second NMOS transistor 120 is coupled to the ground terminal (VSSA) 180.
Wherein the gate of the first PMOS transistor 140 is coupled to the drain of the first NMOS transistor 110, the gate of the second PMOS transistor 130 is coupled to the drain of the second NMOS transistor 120. Therefore, when the input voltage at the first input terminal 115 turns on the first NMOS transistor 110, the first PMOS transistor 140 is turned on and there is an output voltage generated at the first output terminal 145. When the input voltage at the second input terminal 125 turns on the second NMOS transistor 120, the second PMOS transistor 130 is turned on and there is an output voltage generated at the second output terminal 135.
The level shift circuit uses CMOS transistors (PMOS and NMOS transistors), and the PMOS transistors of the CMOS transistors in the circuit are much bigger than the NMOS transistors. Thus, to integrate the PMOS transistors into the chip, the chip must be bigger. Furthermore, the cost of the design and manufacture for CMOS is much more expensive than PMOS. Therefore, a level shift circuit is needed with a new design to reduce the layout space and cost.